1. Field of the Invention
The present invention relates to semiconductor memories and to static memory cells. More particularly, the present invention relates to a high-voltage five-transistor static random access memory cell.
2. The Prior Art
CMOS Static Random Access Memory (SRAM) cells are known in the art. A typical prior-art SRAM cell is found in a memory product designated 5101 and manufactured by Intel Corporation of Santa Clara, Calif. The SRAM cell in this product includes six transistors, four of which constitute a cross-coupled latch, and two of which constitute gating devices used to couple the latch to two bit lines (data lines) when the memory cell is selected. These two bit lines are typically connected to a differential amplifier which amplifies the difference in voltage levels on the bit lines. The amplified difference is then interpreted as a logical 0 or a logical 1, according to some design convention.
To write a bit into the memory cell, the memory cell is selected and its bit lines are charged to opposite states by a write driver circuit. The six-transistor prior-art SRAM memory cell requires two gating devices (pass transistors) and two bit lines to be reliably read and written.
In certain applications, it is desirable to provide a high-voltage SRAM memory cell. To implement a high-voltage SRAM memory cell using prior-art techniques involves using a desired signal as an input to a level-shifter circuit which is used to develop a new high-voltage-level signal at its output. The high-voltage potential may be, for example, a programming voltage level (V.sub.HS), a power-supply voltage level or a charge pump voltage. Prior-art circuits for performing this function are characterized by static power consumption.